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http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 1 wenshing?? t rw -24l01 module 2.4g ism transceiver version history version date changes v1.00 august 15, 2013 1 st. edition
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 2 key features ? worldwide 2.4ghz ism band operation ? 250kbps, 1mbps and 2mbps on air datarates ? ultra low power operation ? programmable power:, - 25, - 15, - 5, 0, 5 dbm ? 900na in power down ? 26a in standby - i ? rf chip drop - in compatibility with nrf24l0 ? low cost ? 1.9 to 3.6v supply range ? enhanced shockburst ? ? automatic packet handling ? auto packet transaction handling ? 6 data pipe multiceiver ? applications ? wireless pc peripherals ? mouse, keyboards and remotes ? 3 - in - 1 desktop bundles ? advanced media center remote controls ? toys ? game controllers ? sports watches and sensors ? rf remote controls for consumer electronics ? home and commercial automation ? ultra low power sensor networks ? active rfid ? asset tracking systems size view
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 3 2 . 4 ghz 5 dbm modem fifo packet handler crc temp frame gan digital logic trw - 24 l 01 function block diagram rf chip rx filter 8 irq 7 miso 6 mosi 4 csn 3 ce 2 vdd 1 gnd 5 sclk block diagram 1 pin function pin name i/o description 1 gnd gnd ground . 2 vcc input +1.8 to + 3.6 v supply voltage input to internal regulators 3 ce digital input chip enable activates rx or tx mode 4 csn digital i nput spi chip select 5 sck digital input spi clock 6 mosi digital input spi slave data input 7 miso digital output spi slave data output with tri - state option 8 irq digital output mask able interrupt pin. active low
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 4 2 hardware specification 2.1 specification conditions: vdd =vcc = + 3.3 v, vss = 0v, ta = 25 o c parameter description min typ max unit vdd supply voltage range 1.9 3.3 3.6v v ipd power down current 9 ua istby standby current 47 ua freq operating frequency 2400 2484 mhz fspace channel spacing 1 mhz fxtal crystal frequency 16 mhz tolxtal crystal tolerance - 60 60 ppm fd250k frequency deviation @250kbps 1000 khz fd1m frequency deviation @1mbps 1100 khz fd2m frequency deviation @2mbps 2500 khz t_trx standby to tx/rx time 130 us idc_txmid tx dc current, 0dbm output pow e r 20.5 ma idc_txmin tx dc current, minimum output power 10.8 ma idc_rx rx dc current consumption 26.6 ma pmax output power at maximum power 5 dbm pmin output power at minimum power - 40 dbm pacc power accuracy 2 db sens_250 sensitivity <0.1% ber 250kbps - 92 dbm sens_1m sensitivity <0.1% ber 1mbps - 90 dbm sens_2m sensitivity <0.1% ber 2mbps - 88 dbm ci_250 co - channel rejection c/i @ 250kbps 3 db ci_1m co - channel rejection c/i @ 1mbps 5 db ci_2m co - channel rejection c/i @ 2mbps 8 db blk1m_1 1mbps c/i in - band block 1mhz offset - 2 db blk1m_2 1mbps c/i in - band block 2mhz offset - 21 db blk1m_3 1mbps c/i in - band block 3mhz offset - 24 db blk2m_2 2mbps c/i in - band block 2mhz offset - 21 db blk2m_4 2mbps c/i in - band block 4mhz offset - 22 db blk2m_6 2mbps c/i in - band block 6mhz offset - 35 db
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 5 3 control states 3.1 state diagram trw - 24l01 can be set up as a primary transmitter (ptx) or a primary receiver (prx). a transmission pair must be set up as a ptx and a prx, i.e. 2 ptxs cannot communicate with each other, and neither can two prxs. ptx/prx is setup by the rx_on bit. setting 0 makes d evice a ptx, and setting 1 makes device a prx. figure 3 shows the typical state diagram of trw - 24l01 with auto - acknowledgement (auto - ack) feature disabled. operation states are fully controlled by the mcu through the power vdd , hardwire pin ce , and regis ter bits pwr_on and rx_on. when auto - ack is enabled, ptx automatically switches to rx mode to receive the ack packet, switching back to tx for retransmission if necessary; prx automatically switches to tx mode to send the ack packet. figure 4 shows the p tx state diagram in auto - ack mode, and figure 5 shows the prx state diagram in auto - ack mode. figure 3: trw - 24l01 state diagram 3.1.1 power - on reset when power is applied to vdd and is over 1.9v threshold, trw - 24l01 will run power - on reset. once power - on reset is completed, the device will be in power - down mode. 3.1.2 power - down mode in power - down mode, trw - 24l01 is in deep - sleep and only the spi interface is active. trw - 24l01 i s in power - down mode when pwr_on is set to 0.
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 6 figure 5: ptx with auto - ack figure 4: prx with auto ack the device enters power - down mode whenever pwr_on is set to zero. 3.1.3 standby mode setting pwr_on bit to ?1? will activate device to standby mode (while ce remains 0). in standby mode, the crystal oscillator is active, and the device is ready to quickly enter tx or rx mode.
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 7 3.1.4 tx mode trw - 24l01 transmits packets in tx mode. to operate in tx mode, the device needs to be set up as a ptx (rx_on=0), standby mode (pwr_on=1), and a payload(s) in fifo. there are two modes of tx: pulsed (single packet mode) and continuous mode. a ce high pulse of at lea st 10 us triggers a single packet to be sent. keeping ce high will set the device to continuous tx mode, which will send out all packets in fifo. after fifo is emptied, the device will power - off radio and digital baseband to save current, but the device wi ll commence transmission as soon as a new payload enters fifo. when auto - ack feature is enabled, a prx device automatically enters tx mode to send back an ack packet after a valid packet is received from a ptx. 3.1.5 rx mode trw - 24l01 receives packets in rx mode. the device needs to be set up as a prx (rx_on=1) and in standby mode (pwr_on=1). pulling ce pin high sets the device to rx mode and will continue listening for packets as long as ce is held high. payloads of valid packets will be placed into the rx fifo. when auto - ack feature is enabled, a ptx device automatically enters rx mode after transmission to listen for an ack packet from the prx. 3.2 radio setup trw - 24l01 supports 250kbps, 1mbps, and 2 mbps air bit rate. the choice of which bit rate to use depends on range, current consumption, and data rate needed. lower bit rate has longer range, while higher bit rate has lower current consumption and reduced probability of in - air collision. air rate is set by the setup_rf register. the channel may be set in 1 mhz increment from 2400 mhz to 2484 mhz. although it is possible to set the channel frequency higher than 2484 mhz, it is not recommended for this may violate reg ional regulations. for 250kbps and 1mbps operation, the channel may be set in 1 mhz increment; for 2mbps operation, the channel spacing should be 2 mhz or more. channel selection is set by the rf_ch register. in addition to the device address, the bit ra te and channel frequency need to be set the same for the radios to communicate with each other. 3.3 rssi recorder trw - 24l01 features an advanced rssi block and control, allowing the receiver host to collect detailed information of the current rx channel. there are two decision thresholds that can be individually set. an rssi recorder generates a log of the channel traffic. with two decision thresholds, the host can separate the receiving signal into three ranges: low, medium, and high. the rssi recorder c onsists of two 8 - bit shift registers corresponding to the two thresholds, and it keeps track of the rssi readings for the past 8 time slots. a single time slot is 128 us. this advanced rssi
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 8 scheme can be useful in detecting complex channel behaviors such a s fading, interference, and may assist mcu in channel selection. the rssi enable setting and rssi readout are in the rssi register setting. the rssi threshold and recorder are in address 0x18. figure 6 shows the basic concept of the rssi recorder scheme. at read point 1, [rssi1, rssi2] readout will be [0,0], rssirec1 readout will be 0xf8 and rssirec2 readout will be 0x60; at read point 2, [rssi1, rssi2] will read [0,1], rssirec1 will read 0x0f and rssirec2 will read 0x08. trw - 24l01 also has a unique iden tifier encoded in [rssirec2, rssirec1] and can be read right after por. the 16 - bit unique id for trw - 24l01 is 0x7241. to save current, the rssi is set to be off by default. to turn on the rssi, enable bit 4 of the rssi register. the two decision threshol ds are also indicated at bit 0 and bit 1 of the rssi register. figure 6: rssi recorder scheme 4 packet information figure 7: packet format the packet consists of 5 portions: preamble, address, packet control, payload, and crc. the preamble, address, and payload are required fields; packet control and crc are optional fields, depending on settings. 4.1 packet format
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 9 4.1.1 preamble the preamble is a one - byte alternating sequence of 01010101 or 10101010, depending on the first bit in the address. if the first address bit is 1 the preamble will be set to 10101010; if the first address bit is 0, the preamble is set to 01010101. 4.1.2 address this field holds the address of the receiver. addresses with only one or two transitions (e.g. 0x000005ffff or 0x00ff000000) or as a continuation of the preamble (010101?) are not recommended for they may increase the packet error rate. 4.1.3 p acket control the packet control field consists of 9 bits, containing a 6 - bit payload length field, a 2 - bit packet identity (pid) field, and a one - bit no_ack flag. the payload length is used when dynamic payload length feature is enabled. it specifies p ayload length in bytes, which can range from 1 to 32. values higher than 32 are ignored. the pid field is used to detect whether the packet is new or retransmitted. this field prevents the prx from delivering the same payload more than once to the rx hos t mcu. the pid is incremented at the tx side for each new packet received through the spi. the pid and crc fields are used together by the prx to determine whether the received packet is retransmitted or new. the no_ack flag is used when the auto - ack feat ure is enabled. setting the flag high tells the receiver that this packet does not need to be auto acknowledged. this flag is set on the ptx by using the command w_tx_pload_noack, instead of w_tx_pload, to write the tx payload. to use this function require s enabling the en_dyn_ack bit in the feature register. when this option is used to transmit, the ptx goes directly to standby mode after transmitting the packet, and the prx will not transmit an ack packet after the packet is received. 4.1.4 payload the payload can be 1 to 32 bytes wide. the payload can be set either static or dynamic in length, defined by the packet control field. the default setup is static payload length. the static payload length is set by the rx_pw_px register on the receiver side. p ayload length on the transmitter side is set by the number of bytes placed in the tx_fifo and must be equal to the value set in the rx_pw_px register on the receiver side. dynamic payload length enables the transmitter to send packets of variable length to the receiver. the receiver can decode the payload length automatically from the control field value. the mcu can read the received payload length by using r_rx_pl_wid command. to enable dynamic payload, set the en_dpl bit in the feature register to 1. in rx mode, the dynpd register must be set. a ptx that transmits to a prx with dynamic
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 10 payload enabled must have the dpl_p0 bit in dynpd set. 4.1.5 cyclic redundancy check (crc) the crc is an error detection mechanism in the packet. it can be set to 1 or 2 bytes and is calculated over the address, packet control field, and payload. the polynomial for 1 - byte crc is x 8 + x 2 + x + 1, with an initial value of 0xff. the polynomial for 2 - byte crc is x 16 + x 12 + x 5 + 1, with an initial value of 0xffff. the crcc bit in the cfg_top register sets the crc length, and en_crc controls whether crc is used. the crc is a mandatory field for packets with auto - ack or dynamic payload length ena bled, and will override the en_crc bit setting. if crc is enabled, packets will be dropped if crc fails. 4.2 packet handling in tx mode, the phy engine fetches a payload from tx fifo, assembles the payload into a packet and transmits the packet in a shor t burst. after transmission, if the ptx packet has the no_ack flag set, the device sets tx_ds to 1 and gives an active low interrupt irq to mcu. if the ptx packet is an auto - ack one, the ptx needs to receive an ack from the prx and then asserts the tx_ds i rq. the receiver continuously listens to the air channel for radio signal, and once it is synchronized to a likely signal, the phy engine will validate the address and crc of the possible packet. if a valid packet is detected and is a new one, the phy eng ine writes the payload to rx fifo, sets rx_dr to 1 and gives an active low interrupt irq to mcu. when auto - acknowledge is enabled (en_aa=1), the ptx will enter rx mode after transmission to wait for an ack packet. if an ack is not received within delay se t by ard[3:0], the ptx re - transmits the original packet and enters rx mode to wait for ack. the above action is repeated until an ack packet is received or the number of re - transmission exceeds a threshold set by arc[3:0]. if the latter threshold is met, t he ptx will set max_rt to 1 and give an active low interrupt irq to mcu. two packet loss counters (arc_cnt and plos_cnt) are incremented each time a packet is lost. the arc_cnt counts the number of retransmissions for the current transaction. the plos_cnt counts the total number of retransmissions since the last channel change. initiating a new transmission resets the arc_cnt. writing to the rf_ch register resets the plos_cnt. the arc_cnt and the plos_cnt are in the observe_tx register. they may be used as an indicator of overall channel quality. the ptx device will retransmit if its rx fifo is full but receives an ack packet with payload. as an alternative for the ptx to auto retransmit, it is possible to manually set the device to retransmit a packet a nu mber of times. this is done by the reuse_tx_pl command. when auto - ack is enabled, it is possible for the prx to send a payload along with the ack packet. to use this feature, the en_ack_pay bit in the feature register needs to be set. in addition, the dyn amic payload function also needs to be set. the mcu at the prx needs to upload the payload to the prx?s tx fifo by using the w_ack_payload command. payloads pending in the tx fifo (of the prx) will be sent after a new packet is received from ptx. up to thr ee payloads may be pending in the tx fifo (of the prx) at the same time.
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 11 5 data and control interface 5.1 tx and rx fifo trw - 24l01 has three levels of fifo for the transmitter, and three levels of fifo for receiver. each fifo level is 32 bytes in length . the tx fifo is used to store payloads that are to be transmitted, and the rx fifo is used to store the received payloads that have not been downloaded by the host mcu. up to three payloads may be stored in a tx fifo, and up to three payloads may be store d in an rx fifo. the rx fifo will also record which data pipe the payload comes from. data pipe information is in the status register and is read out from miso during every spi command. successful transmission of a payload will clear a slot in the tx fifo, and a reading from rx fifo will clear an rx payload slot. both fifos are accessed through the spi using dedicated commands. data access to the two fifos, as the name suggests, follows the first - in first - out principle. in a prx device, the tx fifo can sto re payloads of ack packets for up to three different ptx devices. the tx fifo in a prx may be filled up and blocked if all pending payloads are addressed to the pipe where the link to the ptx is lost. in this case, the mcu should flush the tx fifo by using the flush_tx command. the tx fifo may be accessed using three different commands: w_tx_pload, w_ack_pload, and w_tx_pload_noack. all three commands access the same tx fifo. the description of the commands is detailed in the spi command section. the rx fi fo is accessed by the command r_rx_pload, and it may be accessed in both ptx and prx mode. the payload width of the top slot in rx fifo is read by the command r_rx_pl_wid. the statuses of the tx fifo and rx fifo are in the status_fifo register. the device may also be configured to read out the status_fifo register during every command by adjusting the stat_setup setting in feature register. the device may retransmit its last transmitted payload by the command reuse_tx_pl and pulsing the ce pin to trigger transmission. payload reuse will remain active until w_tx_pload or flush_tx command is executed. 5.2 interrupt trw - 24l01 ?s pin 8 is an active - low interrupt pin, used to inform host mcu of various events. interrupt is activated when the tx_ds, rx_dr, or m ax_rt in the status register is set high. the irq pin is reset when the host writes ?1? to the irq source bit in the status register. in the config register, there are three mask bits, which may be used to set which event triggers the irq pin. by default a ll irq sources are enabled. please note that the 3 - bit pipe information in the status register is updated during the irq pin transition. the pipe information is unreliable if the status register is read during the irq pin high - to - low transition. 5.3 star connection trw - 24l01 may be configured as a prx receiving from up to 6 ptx devices, forming a star network. once configured, the connections are presented as different data pipes to the prx host. the following settings are common to all data pipes: ? crc on/off (always enabled when using auto - ack or dynamic payload) ? crc setting (1 or 2 bytes) ? rx address width ? frequency channel ? air data rate
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 12 data pipes are enabled with the en_rxaddr register. by default data pipe 0 and 1 are enabled. data pipe addresse s are configured in the rx_addr_px register, where ?x? is from 0 to 5. each data pipe should have a unique address. data pipe 0 has a unique address. addresses of data pipes 1 to 5 differ only by the lsbyte. during a star connection, since the prx device will be transmitting ack packets to different ptx devices, to identify the correct destination, the prx device uses the rx address of the particular pipe as the packet address when sending ack packets. therefore for the ptx devices, their rx address needs to be set the same as their tx address. furthermore, since all data pipes operate at the same channel frequency, only one data pipe should be active at anytime. when multiple ptxs are transmitting to a prx, the ard may be set at different values so that co llisions happen only once. 5.4 spi command trw - 24l01 is controlled by a standard spi interface. all commands must be initiated by a high to low transition on pin csn . the status of the chip is shifted out on the miso pin simultaneously as the spi command word is serially fed into the mosi pin. typically the status output is the status register bits, but it can be configured to report rx status or fifo status. the output of the miso pin is set by the stat_setup in the feature register. the spi command format consists of an 8 - bit command word (from msb to lsb) followed by the data in bytes. data bytes are fed from lsbyte to msbyte, and start with the msbit in each byte first. the r_ reg and w_reg commands operate on single or multi - byte registers. when accessing multi - byte registers, writing of bytes may be terminated before all bytes are written, leaving unwritten msbyte(s) unchanged. note: the 3 bit pipe information in the status r egister is updated when irq pin changes from high to low. therefore, the pipe information is unreliable if the status register is read during an irq transition. table 1: spi commands command name command word (binary) data bytes operation r_registe r 000a aaaa 1 to 5 lsbyte first read command and status registers. aaaaa = 5 bit register map address w_regist er 001a aaaa 1 to 5 lsbyte first write command and status registers. aaaaa = 5 bit register map address executable in power down or standby modes only. r_rx_payl oad 0110 0001 1 to 32 lsbyte first read rx - payload: 1 ? 32 bytes. a read operation always starts at byte 0. payload is deleted from fifo after it is read. used in rx mode. w_tx_pay load 1010 0000 1 to 32 lsbyte first write tx - payload: 1 ? 32 bytes. a write operation always starts at byte 0 used in tx payload. flush_tx 1110 0001 0 flush tx fifo, used in tx mode flush_rx 1110 0010 0 flush rx fifo, used in rx mode
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 13 should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. reuse_tx_ pl 1110 0011 0 used for a ptx device reuse last transmitted payload. packets are repeatedly retransmitted as long as ce is high. tx payload reuse is active until w_tx_payload or flush tx is executed. tx payload reuse must not be activated or deactivated during package transmission activate 0101 0000 1 this write command followed by data 0x73 activates the following features: ? r_rx_pl_wid ? w_ack_payload ? w_tx_payload_noack a new activate command with the same data deactivates them again. this is executable in power down or stand by modes only. the r_rx_pl_wid, w_ack_payload, and w_tx_payload_noack features registers are initially in a deactivated state; a write has no effect, a read only results in zeros on miso . to activate these registers, use the activate command followed by data 0x73. then they can be accessed as any other register in trw - 24l01 . use the same command and data to deactivate the registers again. r_rx_ pl_ wida 0110 0000 read rx - payload width for the top r_rx_payload in the rx fifo. w_ack_pa yloada 1010 1ppp 1 to 32 lsbyte first used in rx mode. write payload to be transmitted together with ack packet on pipe ppp. (ppp valid in the range from 000 to 101). maximum three ack packet payloads can be pending. payloads with same ppp are handled using first in - first out principle. write payload: 1 ? 32 bytes. a write operation always starts at byte 0. w_tx_pay load_no acka 1011 000 1 to 32 lsbyte first used in tx mode. disables autoack on this specific packet.
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 14 nop 1111 1111 0 no operation. might be used to read the status register 5.5 spi timing table 2: spi timing symbol parameters minimum maximum units tdc data to sck setup 3 ns tdh sck to data hold 3 ns tcsd csn to data valid 38 ns tcd sck to data valid 55 ns tcl sck low time 40 ns tch sck high time 40 ns fsck sck frequency 0 10 mhz tr/tf sck rise & fall time 100 ns tcc csn to sck setup 3 ns tcch sck to csn hold 3 ns tcwh csn inactive time 50 ns tcdz csn to output high z 38 ns
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 15 5.6 miso status readout by default the miso will readout the status register during every spi command input. a feature of trw - 24l01 is that the miso readout may be set to ?rx? focused readout or ?fifo? readout. the miso readout is set by stat_setup in the feature register. when the register is set to rx readout mode, the positions of max_rt and tx_full are replaced by rssi2 and rssi1. in fifo readout mode, miso will read out status_fifo instead of the status register. 6 register map table addresses 0x19, 0x1a, 0x1b, and 0x1f are reserved for test purposes and performance tuning. altering them to values other than their por values may result in chip m alfunction. reserved bits that are labeled ?unused? do not have any function. reserved bits that are labeled ?only ?0? allowed? are not to be changed. modifications to such reserved bits may result in chip malfunction. address (hex) name bit reset value t ype description 00 cfg_top top - level configuration reserved 7 0 r/w must be 0 for normal operation mask_rx_dr 6 0 r/w mask interrupt caused by rx_dr; 1: interrupt not reflected on irq pin; 0: reflect rx_dr as active low interrupt on irq pin mask_tx_ds 5 0 r/w mask interrupt caused by tx_ds; 1: interrupt not reflected on irq pin; 0: reflect tx_ds as active low interrupt on irq pin mask_max_rt 4 0 r/w mask interrupt caused by max_rt; 1: interrupt not reflected on irq pin; 0: reflect max_rt as active low interrupt on irq pin en_crc 3 1 r/w enable crc. forced high if any of the bits in en_aa is high crcc 2 0 r/w crc scheme 0: 1 byte, 1: 2 bytes pwr_on 1 0 r/w 1: power - up, 0, power - down rx_on 0 0 r/w 1: prx, 0: ptx 01 en_aa auto - acknowledgement settings reserved 7:6 0 r/w unused enaa_p5 5 1 r/w enable aa on data pipe 5
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 16 enaa_p4 4 1 r/w enable aa on data pipe 4 enaa_p3 3 1 r/w enable aa on data pipe 3 enaa_p2 2 1 r/w enable aa on data pipe 2 enaa_p1 1 1 r/w enable aa on data pipe 1 enaa_p0 0 1 r/w enable aa on data pipe 0 02 en_rxaddr enable rx addresses reserved 7:6 0 r/w unused enrx_p5 5 1 r/w enable data pipe 5 enrx_p4 4 1 r/w enable data pipe 4 enrx_p3 3 1 r/w enable data pipe 3 enrx_p2 2 1 r/w enable data pipe 2 enrx_p1 1 1 r/w enable data pipe 1 enrx_p0 0 1 r/w enable data pipe 0 03 setup_aw address width & timing setup reserved 7: 4 0 r/w unused reserved 3 : 2 11 r/w reserved setting, must be set to 11 reserved 1 : 0 11 r/w reserved setting, must be set to 11 04 setup_retr automatic retransmission setup ard[3:0] 7:4 0000 r/w automatic retransmission delay 0000: wait 250us 0001: wait 500us ? 1111: wait 4000us delay defined as ?? arc[3:0] 3:0 0011 r/w auto retransmit count 0000: disabled 0001: up to 1 re - transmit on fail of aa ? 1111: up to 15 re - transmits on fail of aa 05 rf_ch rf channel reserve 7 0 r/w unused rf_ch[6:0] 6:0 0x02 r/w set frequency channel in 1 mhz increment, 0x00 is 2400 mhz 06 setup_rf rf settings
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 17 en_cw 7 0 r/w enable continuous carrier when set high confirm during chip verification en_prbs 6 0 r/w enable prbs bit stream when set high; en_cw also needs to be enabled rf_dr_low 5 0 r/w see rf_dr_high tx_attn 4 0 r/w tx low - power mode confirm actual attenuation level rf_dr_high 3 0 r/w [rf_dr_low, rf_dr_high] 00: 1mbps 01: 2mbps 10: 250kbps 11: reserved rf_pwr[1:0] 2:1 01 r/w set rf output power in tx mode 00: - 18 dbm 01: - 12 dbm 10: - 6 dbm 11: 0 dbm reserved 0 0 r/w unused 07 status status (read - out from miso pin during spi command word input); miso output may be adjusted reserved 7 0 r/w unused rx_dr 6 0 r/w data ready rx fifo interrupt. asserted when new data arrives at rx fifo. write 1 to clear bit tx_ds 5 0 r/w data sent tx fifo interrupt. asserted when packet transmitted. if auto - ack is activated, this bit is set high only when ack is received. write 1 to clear bit max_rt 4 0 r/w maximum number of tx retransmit interrupt. write 1 to clear bit. if max_rt is
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 18 asserted it must be cleared to enable further operation rx_p_no[2:0] 3:1 111 r data pipe number for the payload available for reading from rx_fifo 000~101: data pipe number (0~5) tx_full 0 0 r 0: tx fifo available 1: tx fifo full 08 observe_tx transmission observation plos_cnt[3:0] 7:4 0000 r count lost packets. overflow protected to 15, and stops at maximum value until reset. counter reset by writing to rf_ch arc_cnt[3:0] 3:0 0000 r count retransmitted packets. counter resets when transmission of a new packet starts 09 rssi tssi and rssi indicator/control reserved 7 0 r/w must be 0 for normal operation reserve 6 0 r/w must be 0 for normal operation reserved 5 0 r/w must be 0 for normal operation en_rssi 4 0 r/w enable rssi reserved 3 0 r reserved register readout reserved 2 0 r reserved register readout rssi2 1 0 r rssi indicator at threshold 2 rssi1 0 0 r rssi indicator at threshold 1 0a rx_addr_p0 39:0 0xe7e7e7 e7e7 r/w rx address data pipe 0. 5 bytes maximum. lsb byte written first. number of bytes used set by setup_aw. 0b rx_addr_p1 39:0 0xc2c2c2 c2c2 r/w rx address data pipe 1. 5 bytes maximum. lsb byte written first. number of bytes used set by setup_aw. 0c rx_addr_p2 7:0 0xc3 r/w rx address data pipe 2. only lsb are set, msb
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 19 bytes use rx_addr_p1[39:8] 0d rx_addr_p3 7:0 0xc4 r/w rx address data pipe 3. only lsb are set, msb bytes use rx_addr_p1[39:8] 0e rx_addr_p4 7:0 0xc5 r/w rx address data pipe 4. only lsb are set, msb bytes use rx_addr_p1[39:8] 0f rx_addr_p5 7:0 0xc6 r/w rx address data pipe 5. only lsb are set, msb bytes use rx_addr_p1[39:8] 10 tx_addr 39:0 0xe7e7e7 e7e7 r/w tx address. used for ptx only. set rx_addr_p0 equal to this address to handle auto acknowledgement 11 rx_pw_p0 reserved 7:6 00 r/w unused rx_pw_p0 5:0 0 r/w number of bytes in rx payload in data pipe 0 (1 to 32). 0: pipe not used 12 rx_pw_p1 reserved 7:6 00 r/w unused rx_pw_p1 5:0 0 r/w number of bytes in rx payload in data pipe 1 (1 to 32). 0: pipe not used 13 rx_pw_p2 reserved 7:6 00 r/w unused rx_pw_p2 5:0 0 r/w number of bytes in rx payload in data pipe 2 (1 to 32). 0: pipe not used 14 rx_pw_p3 reserved 7:6 00 r/w unused rx_pw_p3 5:0 0 r/w number of bytes in rx payload in data pipe 3 (1 to 32). 0: pipe not used 15 rx_pw_p4 reserved 7:6 00 r/w unused rx_pw_p4 5:0 0 r/w number of bytes in rx
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 20 payload in data pipe 4 (1 to 32). 0: pipe not used 16 rx_pw_p5 reserved 7:6 00 r/w unused rx_pw_p5 5:0 0 r/w number of bytes in rx payload in data pipe 5 (1 to 32). 0: pipe not used 17 status_fifo reserved 7 0 r/w unused tx_reuse 6 0 r used for a ptx device pulse the rfce high for at least 10s to reuse last transmitted payload. tx payload reuse is active until w_tx_payload or flush tx is executed. tx_reuse is set by the spi command reuse_tx_pl, and is reset by the spi commands w_tx_payload or flush tx *rewrite tx_full 5 0 r 1: tx fifo full 0: available slots in tx fifo tx_empty 4 1 r 1: tx fifo empty 0: data in tx fifo reserved 3:2 0 r reserved register readout rx_full 1 0 r 1: rx fifo full 0: available slots in rx fifo rx_empty 0 1 r 1: rx fifo empty 0: rx fifo full 18 rssirec rssi recorder feature reserved 31:26 111 w reserved reserved 25:22 0110 r reserved rx_vref2_sel[2:0] 21:19 000 w rx rssi vref2 setting 000: - 59 dbm, +4db/step 111: out of range rx_vfef1_sel[2:0] 18:16 000 w rx rssi vref1 setting 000: - 69 dbm, +4db/step rssirec2[7:0] 15:8 01110010 r rssi2 recorder, msb is most recent recording, any
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 21 write command on this register will flush rssi setting; when rx_on=0, pwr_on=0 & ce=0, register will read chip id rssirec1[7:0] 7:0 01000001 r rssi1 recorder, msb is most recent recording, any write command on this register will flush rssi setting; when rx_on=0, pwr_on=0 & ce=0, register will read chip id 1c dynpd dynamic payload length reserved 7:6 00 r/w unused dpl_p5 5 0 r/w set 1 to enable dynamic payload length data pipe 5 (requires en_dpl & enaa_p5) dpl_p4 4 0 r/w set 1 to enable dynamic payload length data pipe 4 (requires en_dpl & enaa_p4) dpl_p3 3 0 r/w set 1 to enable dynamic payload length data pipe 3 (requires en_dpl & enaa_p3) dpl_p2 2 0 r/w set 1 to enable dynamic payload length data pipe 2 (requires en_dpl & enaa_p2) dpl_p1 1 0 r/w set 1 to enable dynamic payload length data pipe 1 (requires en_dpl & enaa_p1) dpl_p0 0 0 r/w set 1 to enable dynamic payload length data pipe 0 (requires en_dpl & enaa_p0) 1d feature features stat_setup[1:0] 7:6 00 r/w adjust the output of miso during command input 00: default, miso output is
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 22 status 01: rx readout mode, the miso output max_rt and tx_full bit is replaced by rssi2 and rssi1 readout 10: fifo readout mode, miso output is status_fifo 11: unused, same as 00 reserved 5:3 000 r/w unused en_dpl 2 0 r/w set 1 enables dynamic payload length en_ack_pay 1 0 r/w set 1 enables payload on ack en_dyn_ack 0 0 r/w set 1 enables the w_tx_payload_noack command 1f reserved reserved register reserved 7:0 0 r/w 8?h00: default settings 7 reference schematics attached reference schematics give an example how to have trw - 24l01 module to work with micro - controller, it might be 8051, chips of microchip or any embedded soc, to communicate with host through rs - 232 interface. u4 is rs - 232 transceiver chip which converts signals level. remark antenna wiring should not be positioned above or under the ground layer, power layer and the other wirings.
http://www.wenshing.com.tw ; http://www.rf.net.tw trw - 24l01 datasheet p. 23 size view

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